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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C External Switching Characteristics (Cont.)
Over Recommended Operating Conditions
-5
-75
-10
Parameter
t PD
t PD_MC
t S
t ST
t SIR
t SIRZ
t H
t HT
t HIR
t HIRZ
t CO
t R
t RW
t PTOE/DIS
Description 1, 2, 3
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay through macrocell
GLB register setup time before clock
GLB register setup time before clock with T-type register
GLB register setup time before clock, input register path
GLB register setup time before clock with zero hold
GLB register hold time after clock
GLB register hold time after clock with T-type register
GLB register hold time after clock, input register path
GLB register hold time after clock, input register path with
zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output enable/disable
Min.
—
—
3.0
3.2
1.2
2.2
0.0
0.0
1.0
0.0
—
—
2.0
—
Max.
5.0
5.5
—
—
—
—
—
—
—
—
3.4
6.3
—
7.0
Min.
—
—
4.5
4.7
1.7
2.7
0.0
0.0
1.0
0.0
—
—
4.0
—
Max.
7.5
8.0
—
—
—
—
—
—
—
—
4.5
9.0
—
9.0
Min.
—
—
5.5
5.5
1.7
2.7
0.0
0.0
1.0
0.0
—
—
4.0
—
Max.
10.0
10.5
—
—
—
—
—
—
—
—
6.0
10.5
—
10.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t GPTOE/DIS Input to output global product term output enable/disable
—
9.0
—
10.3
—
12.0
ns
t GOE/DIS
t CW
t GW
t WIR
f MAX 4
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or high (for
high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
—
2.2
2.2
2.2
—
5.0
—
—
—
227
—
2.8
2.8
2.8
—
7.0
—
—
—
168
—
4.0
4.0
4.0
—
8.0
—
—
125
ns
ns
ns
ns
MHz
f MAX (Ext.) Clock frequency with external feedback, [1/ (t S + t CO )]
—
156
—
111
—
86
MHz
1.
2.
3.
4.
Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
Pulse widths and clock widths less than minimum will cause unknown behavior.
Standard 16-bit counter using GRP feedback.
23
Timing v.3.2
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